Multilayer solar cells with bypass diode protection

ABSTRACT

A multilayer solar cell with bypass diodes includes a stack of alternating p and n type semiconductor layers 10, 11, 12, 13, 14 arranged to form a plurality of rectifying photovoltaic junctions 15, 16, 17, 18. Contact is made to underlying layers by way of a buried contact structure comprising grooves extending down through all of the active layers, the walls of each groove being doped 33, 34 with n-or p-type impurities depending upon the layers to which the respective contact is to be connected and the grooves being filled with metal contact material 31, 32. One or more bypass diodes are provided by increasing the doping levels on either side 10, 13 of one or more portions of the junctions 16 of the cell such that quantum mechanical tunnelling provides a reverse bias characteristic whereby conduction occurs under predetermined reverse bias conditions. Ideally, the doping levels in the bypass diodes is 10 18  atoms/cm 3  or greater and the junction area is small.

FIELD OF THE INVENTION

This application is a 371 of PCT/AU95/00829 filed Dec. 8, 1995.

The present invention relates generally to the field of solar celltechnology and in particular the invention relates to the manufacture ofa solar cell with an integrated bypass diode.

The invention provides a new method for providing protection duringoperation and for potentially increasing manufacturing yield of thesedevices by the incorporation of integral bypass diodes into a multilayerstructure. The features of the multilayer structure make theincorporation of these diodes feasible in a way which would be difficultwith conventional devices.

BACKGROUND OF THE INVENTION

The solar cells with integrated bypass diodes are of particular interestin the manufacture of multilayer solar cell which are the subject ofearlier commonly assigned Australian Patent Application No PM4834entitled "Multiple Layer Thin Film Solar Cells" which is incorporatedherein by reference.

In the prior art a bypass diode is a diode connected in reverse polarityto the diode which constitutes the solar cell. In normal practice, thesebypass diodes are discrete diodes which are physically connected acrossindividual cells or groups of cells by techniques such as soldering. Innormal operation, these bypass diodes are reverse biased and do notinterfere with cell operation. However, when cells have lower currentoutput than others in the system, due to effects such as shadowing orcell damage, these diodes provide a low resistance path around the lowoutput cells. This serves two functions. The first is to preventexcessive reverse voltage building across low output cells which canlead to cell destruction by overheating. The second role is to controlthe disproportionate loss of power output that such a shaded or damagedcell could introduce into the system of interconnected cells. Thepurpose and function of bypass diodes are well understood and widelydiscussed in standard texts such as Martin A. Green, "SOLAR CELLS:Operating Principles, Technology and System Applications",(Prentice-Hall, New Jersey, 1982) and S. R. Wenham, M. A. Green and M.Watt, "Applied Photovoltaics", (Bridge Printery, Sydney, 1994). Priorart integral bypass diodes serve a similar function although in general,due to their incorporation directly into the solar cell structure, leadto a reduction in the active volume of the cell with a correspondingreduction in performance even when the bypass diode is reverse biased.

Although bypass diodes are generally incorporated to provide protectionand to decrease power losses during operation in the field, a new andadvantageous application of the present invention is to use such diodesto maintain high production yields of modules of interconnected cells byproviding automatic bypass of damaged or poorly performing cells withinthe module. One strategy, well suited to module fabrication where thereis no prior testing of individual cells, is to include a small number ofadditional cells so that a guaranteed minimum output will be achievedeven in the event of a small number of cell failures.

SUMMARY OF THE INVENTION

According to a first aspect, the present invention provides a solar cellincluding a plurality of doped semiconductor regions defining arectifying junction of a photovoltaic cell, at least a portion of thejunction forming a bypass diode having a reverse bias characteristicwhereby conduction occurs under predetermined reverse bias conditions.

According to a second aspect the present invention provides a solar cellincluding a plurality of doped semiconductor regions defining a firstrectifying junction of a photovoltaic cell and a second rectifyingjunction effectively connected in parallel to and with the same polarityas the first rectifying junction, at least a portion of the secondjunction forming a bypass diode having a reverse bias characteristicwhereby conduction occurs under predetermined reverse bias voltageconditions.

The junction portion forming the bypass diode is preferably formed byproviding high doping levels in each of the semiconductor regionsdefining the bypass diode junction such that quantum mechanicaltunnelling occurs when the junction is reverse biased to thepredetermined value.

Preferably, doping levels in the semiconductor regions defining thebypass diode are greater than 10¹⁸ cm⁻³ (atoms/cm³).

In the past the qualities required for the desired reverse biasconduction have been considered detrimental to photovoltaic performanceand have, therefore, been deliberately avoided, even when adjacentheavily doped n-type and p-type regions exist. In the present invention,it is proposed that such properties be deliberately controlled toenhance this effect. Whereas these types of junctions have beendeliberately avoided in the past, they are included in the presentinvention with sufficiently small area to avoid significant impact onthe photovoltaic performance.

For example, in embodiments having bypass diode doping levels that givereverse conduction, with reverse bias voltages less than 3 volts and inparticular less than 1 volt, the total junction area having this levelof doping will be arranged to be small relative to the activephotovoltaic junction area.

In one embodiment of the invention a multilayer, multijunctionphotovoltaic cell is provided with at least one junction region formedas a bypass diode. In this embodiment the bypass diode junction isformed by a pair of layers of the multilayer cell. The bypass junctionmay include the entire junction formed between two adjacent layers ofthe multilayer cell or alternatively the bypass junction may berestricted to a portion of the junction formed between the two adjacentlayers, depending upon the doping level of the bypass junction portion.

Preferably the multilayer structure includes at least three layers ofalternate polarity material defining p-n junctions between each pair ofalternate layers, at least three layers having a thickness which is notsubstantially greater than a minority carrier diffusion length for thedopant concentration of the material in the respective layer.

Preferably the doped layers will have a thickness which is less than theminority carrier diffusion length for the respective doped material.

Cells may be of doped crystalline or polycrystalline silicon, amorphoussilicon and its alloys, cadmium telluride, cadmium sulphide, copperindium diselenide or alloys incorporating gallium and/or sulphur orother semiconductor material. In cells comprising a stack of siliconlayers, relatively thin layers of silicon/germanium alloy could also beincluded. Layers of insulating material such as silicon oxide or nitridecould also be interleaved within the stack.

In embodiments based upon silicon material, typically maximum dopantconcentrations within at least 3 layers of 10¹⁷ atoms/cm³ or more willbe used, with doped layer thicknesses typically in the range of 0.1 to40 μm. In silicon material the dopant concentration will preferably begreater than 10¹⁷ atom/cm³ over at least 50% of the bulk of each layerand more preferably will range between 10¹⁷ and 10¹⁸ atoms/cm³ oversubstantially all of each layer.

In preferred embodiments using silicon material each layer will bebetween 0.2 and 15 microns thick.

In silicon cells the top layer will preferably have a dopantconcentration of 10¹⁸ atoms/cm³ or greater.

According to a further aspect, the present invention provides a methodof forming a thin film solar cell including the step of

(a) forming onto a substrate a plurality of alternatively doped thinlayers of semiconductor material to form at least one rectifying p-njunction,

(b) during the forming step, forming at least one p-n junction portionof the solar cell with doping levels of 10¹⁸ atoms/cm³ in the adjacent pand n type regions forming said portion.

In a preferred embodiment, this aspect further includes the steps of

(c) forming sequentially at least two sets of grooves in the pluralityof layers to expose some or all of the doped layers,

(d) forming in at least one of the grooves a p-type surface region overthe entire surface of the groove or grooves,

(e) forming in at least one other of the grooves an n-type surfaceregion over the entire surface of the respective groove or grooves,

(f) forming a metal contact in each of the grooves respectively to makecontact with the p-type and n-type surface regions. According to yet afurther aspect, the present invention provides a method of forming athin film solar cell including the steps of

(a) forming onto a substrate a plurality of alternatively doped thinlayers of semiconductor material to form at least one rectifying p-njunction, at least one heavily doped portion of one layer of the solarcell having a doping level of greater than 10¹⁸ atoms/cm³,

(b) forming sequentially at least two sets of grooves in the pluralityof layers to expose some or all of the doped layers, at least one of thegrooves passing through and exposing the at least one heavily dopedportion,

(c) forming in at least one of the grooves a p-type surface region overthe entire surface of the groove or grooves,

(d) forming in at least one other of the grooves an n-type surfaceregion over the entire surface of the respective groove or grooves, thesurface of the groove or grooves exposing the heavily doped portionbeing of opposite dopant type to the heavily doped portion and having adoping level, at least in a region adjacent the heavily doped portion,of 10¹⁸ atoms/cm³ or greater.

In a preferred embodiment, this aspect further includes the step of

(e) forming a metal contact in each of the grooves respectively to makecontact with the p-type and n-type surface regions.

Preferably the substrate will be selected from one of, crystalline,polycrystalline or amorphous silicon, graphite, steel, ceramic or glassand the active layers are formed by a process or processes which may beselected from chemical or physical vapour deposition, solution growth,liquid phase epitaxy and plasma deposition and recrystallization.

Preferably also, the layers formed during the forming steps have athickness not substantially greater than the minority carrier diffusionlength of the respective doped material,

In another embodiment of the invention, a photovoltaic cell is provided,the cell having a buried contact arranged to directly contact asemiconductor region of a first dopant type and being separated from aheavily doped region of a second dopant type by a thin heavily dopedlayer of semiconductor material of the first dopant type.

Preferred embodiments of the invention employ a multilayer thin filmsilicon solar cell structure, however, it will be recognised that theprinciple of the invention is also applicable to other material andstructures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described with reference to theaccompanying drawings in which:

FIG. 1 illustrates the basic structure of a solar cell according to thepresent invention, having multiple interleaved n and p-type dopedcrystalline or polycrystalline silicon layers, using buried contacts tomake contact to buried layers;

FIG. 2 illustrates the same solar cell structure as that of FIG. 1 butwith dimensions given for an embodiment using a poor quality siliconmaterial;

FIG. 3 illustrates the basic structure of FIG. 1 with a bypass diodeformed between two adjacent layers within the stack;

FIG. 4 illustrates solar cell structure of FIG. 3 but with the bypassdiode formed by the junction between a doped layer and the doped regionlining the groove wall;

FIG. 5 illustrates a further embodiment of the invention having asimilar structure to that of FIGS. 3 and 4 but with an additional dopedregion incorporated to provide the bypass diode action; and

FIG. 6 illustrates a simpler 3-layer structure also incorporating bypassdiodes.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Referring to FIG. 1, embodiments of the present invention have astructure comprising a plurality of alternate p-type semiconductorlayers 10, 11 and n-type semiconductor layers 12, 13, 14 formingrectifying junctions 15, 16; 17, 18 therebetween. The alternatingsemiconductor layers 10-14 are formed on and supported by a substrate 19which may be selected from crystalline, polycrystalline or amorphoussilicon, graphite, steel, ceramic, glass or any other material ontowhich a thin semiconductor film can be successfully formed. Contacts 31,32 are formed respectively with the n-type layers 12, 13, 14 and thep-type layers 10, 11 by first forming vertical grooves to expose all ofthe layers of active semiconductor material and then, for those contactswhich are connecting n-type regions, forming a vertical n-type dopedlayer 33 which connects with all of the n-type layers 12, 13, 14 andestablishes a junction with all of the p-type layers 10, 11. Similarly,a p-type doped layer 34 is formed in the groove for the contactconnecting the p-type layers 10, 11, the vertical p-type layer 34establishing a junction with the exposed n-type layers 12, 13, 14. Themetal contacts 31, 32 are then formed within the grooves lined by then-type and p-type layers 33, 34.

The active semiconductor layers 10-14 shown in FIG. 1 are thin filmswhich may be formed on the substrate 19 by any of a number of knowntechniques, including chemical vapour deposition, solution growth,liquid phase epitaxy and plasma deposition and recrystallization, withthe dopant being incorporated in each case during or after the layerformation step.

The multilayer solar cell described with reference to FIGS. 1 and 2offers sufficient flexibility in the selection of the properties of thelayers within the completed cell to allow bypass diodes to beincorporated into the cell in a novel way as part of the basic cellprocessing. Specifically, the bypass diodes are implemented inmultilayer cell embodiments by using junctions between regions which areheavily doped with silicon to values of dopant concentration greaterthan 10¹⁸ cm⁻³. The bypass action of the diode is obtained by using thereverse characteristics of junctions formed between such heavily dopedregions. When such junctions are reverse biased, the energies of theconduction and valence band in the n- and p-type region respectivelyoverlap, in that electrons in both have the same energy. When bothn-type and p-type regions are heavily doped, electrons are able totransfer from the valence band in the p-type material to the conductionband in the n-type material by quantum mechanical tunnelling processes.These become more efficient as the reverse bias across the junctionincreases and the electric field strength in the junction region betweenthe n-type and p-type regions correspondingly increases, giving goodconduction in the reverse bias direction of the diode. The properties ofsuch heavily doped junctions are discussed in standard texts such as S.M. Sze, "Physics of Semiconductor Devices", Wiley, New York, 1981. Theseproperties, however, allow a junction of the same polarity as that ofthe main cell to provide the same protection as normally provided by abypass diode of reverse polarity.

A possible complication, however, is that shunting of this junction orrecombination through the junction at normal operating voltages for themain solar cell, will cause degradation to the main cell performance.These losses can be kept to negligible levels by appropriatelycontrolling the dimensions of the aforementioned heavily doped diode(particularly junction area), its location and to some extent thecorresponding doping concentrations. In the multilayer solar cells, thiscan be achieved without significantly adding to the cost or complexity.

In comparison to the use of prior art integral bypass diodes of oppositepolarity, some embodiments of the present bypass diode approach can beincorporated into multilayer solar cells without significantlysacrificing any of the active volume of the solar cell. Consequently,even in the event of trouble free operation for all cells in a module, asmaller penalty is paid in terms of module performance and cost as aresult of including such diodes.

The multilayer cell provides opportunities for incorporation of suchdiodes which are not present in conventional devices. In one embodimentof the invention illustrated in FIG. 3, diodes with these properties canbe formed between adjacent layers within the multilayer stack byselecting appropriate properties for these adjacent layers, particularlyin relation to their doping levels. Due to the flexibility in design ofmultilayer devices, this can be achieved without severe detriment to theperformance of the overall device. For example, very heavily dopedlayers can be made very thin to maintain their minority carriercollecting ability.

In a second embodiment of the invention illustrated in FIG. 4, the diodewith the required properties can be formed between the doped layerlining the groove walls present within the multilayer structure and oneor more layers within the multilayer stack.

In a third embodiment of the invention illustrated in FIG. 5, the diodewith the required properties can be provided by incorporating additionaldoped regions as further described. This approach would also be suitablefor multilayer devices which do not have grooves.

Referring to FIG. 3, this enhanced embodiment of the present inventionhas a structure identical to that of FIGS. 1 and 2 with the exceptionthat one pair of layers 10, 13 have been selected to be more highlydoped than the other layers 11, 12, 14, to provide a diode junction 16with the desired reverse bias characteristics. Best bypassing actionwill be obtained when these layers are very heavily doped. However,excessive doping can be detrimental to the performance of the solar cellduring normal operation. If both layers are doped above 5×10¹⁹ cm⁻³, itis possible for the overlap of the bands previously mentioned to occurat zero bias and current flow across the diode junction 16 by quantummechanical tunnelling will occur even when it is forward biased. Thiswill subtract from the photocurrent generated by the cell and maydecrease the cell performance under normal operating conditions.Minority carrier properties of the material also decrease withincreasing doping level, rendering these regions less effective asactive cell material. Values of doping above 10²⁰ /cm³ could, however,be accommodated if the total junction area with such values were small(as in the embodiment of FIGS. 4 and 5).

An additional advantage which also follows from the use of such heavilydoped layers is their gettering ability. Heavily doped phosphorus layersin particular are known to be very effective in gettering defects andimpurities from neighbouring regions. By having a number of such heavilydoped layers interspersed within the stack, impurities would be getteredto the internal regions of these layers. Gettering to internal regionswas not previously possible in solar cells. However, by having multipleregions providing multiple gettering layers, the gettered impurities canbe concentrated in regions where they will do least harm to the overalldevice performance. Gettering of impurities and defects from junctiondepletion regions is particularly important in low quality material.

The method of forming the bypass diode effect shown in FIG. 3 would alsobe applicable to other methods of contacting the layers apart from thosedependent on the grooves and would be applicable for implementationswhere the groove was absent.

Rather than having the entire layer heavily doped as shown in FIG. 3,only the region near the junction 17 need to be heavily doped. Thiswould allow the junction with the required properties to be incorporatedwithout sacrificing other desirable properties of the layers involved.

Similar considerations apply to the embodiment of FIG. 4 where the diodewith the required properties is formed between one or more layers 10 inthe stack and the doped walls 33 of the metallized groove 31 to form ajunction 36. The junction area with appropriate properties is greatlyreduced in this configuration giving more design flexibility. Dopinglevels can be heavier without causing problems of the same severity aspreviously described. The regions of interception of the layers with thegroove walls where doping levels are highest on both sides willautomatically become the areas of highest current density and providethe most effective bypass diode action. Again, the distributed getteringbenefits previously mentioned are applicable to this case.

In the third embodiment of FIG. 5, an additional layer region 37 isprovided in the top layer 12 in order to create the bypass diodejunction 39 with the doped wall region 38 of the metallized groove 32.In this case, a separate heavily diffused region is added in the area 37close to the groove. Alternatively, properties of the layers may bemanipulated in other ways to give higher doping density in chosen areas.This approach is also applicable to structures without the metallizedgroove 31, 32.

The device of FIG. 6 resembles a more conventional solar cell. In thiscase, similar techniques can be used to form the bypass diode in thecontact regions. In the case shown, the junction 49 is formed betweenthe n-type region 41 of the rear "floating" junction 47 and the p-typecontact areas 45 within the grooves and the diffused region of thegrooves on the rear surface of the cell. In this instance, current isable to flow between the n-type layers by junction interaction in asimilar manner to a phototransistor where the base current is providedby the light generated carriers. Similar techniques could be used if therear junction was not "floating" but was contacted either directly orvia contact paths through the substrate to the front contact. Again,similar implementations not relying on the presence of the grooves wouldbe possible.

A process which can be used for the manufacture of the cell structure ofFIG. 3 could have the following process steps:

1. Prepare substrate onto which the cell is to be deposited.

2. Deposit an n-type silicon layer by Chemical Vapour Deposition (CVD).

3. Deposit a p-type silicon layer over the previous layer by CVD.

4. Deposit an n-type silicon layer over the previous layer by CVD, thislayer having a minimum doping level of 10¹⁸ atoms/cm³ of the junctionwith the next deposited layer.

5. Deposit a p-type silicon layer over the previous layer by CVD, thislayer having a minimum doping level of 10¹⁸ atoms/cm³ at the junctionwith the previous layer.

6. Deposit an n-type silicon layer over the previous layer by CVD.

7. Apply a masking/surface passivating layer.

8. Form a first set of grooves by either laser or mechanical scribingfollowed by groove cleaning.

9. Form an n-type doped layer on the walls of first groove by diffusionor CVD.

10. Apply a masking layer to wall surfaces of the first groove.

11. Form a second set of grooves followed by groove cleaning.

12. Form a p-type doped layer on the walls of the second groove bydiffusion or CVD.

13. Chemically etch to expose silicon in the grooves.

14. Electroless plating of nickel to contact silicon in the grooves.

15. Sintering of nickel.

16. Apply copper conductors by electroless plating of copper over thenickel.

17. Deposit silver capping layer over the copper.

Although drawings are shown for flat interfaces, in practice these couldbe structured or textured to improve light trapping in cell.

It will be appreciated by those skilled in the art, that variations inthe above with respect to material selection, fabrication techniques,and structure dimensions can be used without departing from the spiritof the invention.

We claim:
 1. A solar cell including at least three doped semiconductorregions defining at least two rectifying junctions of a photovoltaiccell, at least a portion of one of the junctions forming a bypass diodehaving a reverse bias characteristic such that conduction occurs whenthe at least a portion of the one of the junctions is reversed biased bya potential greater than or equal to a reverse bias threshold.
 2. Thesolar cell of claim 1 wherein the junction portion forming the bypassdiode is formed by providing high doping levels in each of thesemiconductor regions defining the bypass diode junction such thatquantum mechanical tunnelling occurs when the at least a portion of theone of the junctions is reversed biased by the potential greater than orequal to the reverse bias threshold.
 3. The solar cell of claim 2wherein the semiconductor regions defining the bypass diode are doped toa level of 10¹⁸ cm⁻³ (atoms/cm³) or greater.
 4. The solar cell of claim3 wherein the at least three doped semiconductor regions include anactive photovoltaic junction area and a total junction area of thebypass diode is arranged to be small relative to the active photovoltaicjunction area.
 5. The solar cell of claim 4 wherein the bypass diode hasa reverse bias conduction voltage of less than 3 volts.
 6. The solarcell of claim 5 wherein the bypass diode has a reverse bias conductionvoltage of less than 1 volt.
 7. The solar cell as claimed in claim 1wherein each of the at least three doped regions is a layer of amultilayer cell and the junction of the bypass diode is formed by anadjacent pair of the layers.
 8. The solar cell of claim 7 wherein thejunction of the bypass diode includes an entire junction formed betweenthe adjacent pair of the layers of the multilayer cell.
 9. The solarcell of claim 7 wherein the junction of the bypass diode is restrictedto a portion of the junction formed between the two adjacent layers. 10.The solar cell as claimed in claim 1 wherein the solar cell includes aburied contact which directly contacts a semiconductor region of a firstdopant type and is separated from a heavily doped region of a seconddopant type by a thin heavily doped layer of semiconductor material ofthe first dopant type.
 11. The solar cell of claim 1, having at leastthree layers formed of alternate polarity material layers defining p-njunctions between each pair of the alternate layers, at least threelayers having a thickness which is not substantially greater than aminority carrier diffusion length for the dopant concentration of thematerial in the respective layer.
 12. The solar cell of claim 11 whereinthe doped layers have a thickness which is less than the minoritycarrier diffusion length for the respective doped material.
 13. Thesolar cell of claim 11 wherein the cell material is selected from one ormore of doped crystalline or polycrystalline silicon, amorphous siliconand its alloys, cadmium telluride, cadmium sulphide, copper indiumdiselenide and its alloys with gallium and sulphur.
 14. The solar cellof claim 11 wherein the solar cell includes a stack of silicon layersand relatively thin layers of silicon/germanium alloy.
 15. The solarcell of claim 11 wherein the solar cell material is silicon, and dopedlayer thicknesses are in the range of 0.1 μm to 40 μm.
 16. The solarcell of claim 15 wherein each layer is between 0.2 μm and 15 μm thick.17. A method of forming a thin film solar cell including the stepsof:(a) forming onto a substrate at least three alternatively doped thinlayers of semiconductor material to form at least two rectifying p-njunctions, and (b) during the forming step, forming at least one p-njunction portion of the solar cell with doping levels of 10¹⁸ atoms/cm³or greater in the adjacent p and n type regions forming said portion.18. The method of claim 17 further including the steps of(c) formingsequentially at least two sets of grooves in the alternatively dopedthin layers of semiconductor material to expose some or all of the dopedlayers, (d) forming in at least one of the grooves a p-type surfaceregion over the entire surface of the groove or grooves, (e) forming inat least one other of the grooves an n-type surface region over theentire surface of the respective groove or grooves, and (f) forming ametal contact in each of the grooves respectively to make contact withthe p-type and n-type surface regions.
 19. The method of claim 17wherein each layer has a thickness not substantially greater than theminority carrier diffusion length of the respective doped material. 20.The method of claim 17 wherein the substrate is selected from one of,crystalline, polycrystalline or amorphous silicon, graphite, steel,ceramic or glass.
 21. The method of claim 17 wherein the alternativelydoped thin layers of semiconductor material are formed by a process orprocesses selected from chemical or physical vapour deposition, solutiongrowth, liquid phase epitaxy and plasma deposition andrecrystallization.
 22. A method of forming a thin film solar cellincluding the steps of (a) forming onto a substrate a plurality ofalternatively doped thin layers of semiconductor material to form atleast one rectifying p-n junction, at least one heavily doped portion ofone layer of the solar cell having a doping level of greater than 10¹⁸atoms/cm³ (b) forming sequentially at least two sets of grooves in theplurality of layers to expose some or all of the doped layers, at leastone of the grooves passing through and exposing the at least one heavilydoped portion, (c) forming in at least one of the grooves a p-typesurface region over the entire surface of the groove or grooves, and (d)forming in at least one other of the grooves an n-type surface regionover the entire surface of the respective groove or grooves, the surfaceof the groove or grooves exposing the heavily doped portion being ofopposite dopant type to the heavily doped portion and having a dopinglevel, at least in a region adjacent the heavily doped portion, of 10¹⁸atoms/cm³ or greater.
 23. The method of claim 22 further including thestep of(e) forming a metal contact in each of the grooves respectivelyto make contact with the p-type and n-type surface regions.
 24. Themethod of claim 22 wherein each layer has a thickness not substantiallygreater than the minority carrier diffusion length of the respectivedoped material.
 25. The method of claim 22 wherein the substrate isselected from one of, crystalline, polycrystalline or amorphous silicon,graphite, steel, ceramic or glass.
 26. The method of claim 22 whereinthe plurality of alternatively doped thin layers of semiconductormaterial are formed by a process or processes selected from chemical orphysical vapour deposition, solution growth, liquid phase epitaxy, andplasma deposition and recrystallization.